1. Field of Invention
This invention relates to a circuit substrate and a fabrication method thereof. More particularly, the present invention is directed to a circuit substrate, suitable for an integrated circuit, and fabrication method thereof.
2. Related Art
Presently, circuit substrate is commonly employed as carrier in electrical industry. Not only circuit substrate is employed as printed circuit board (PCB) but also package substrate, which is applicable to an integrated circuit package. Recently, a high-density circuit substrate having multiple layers and conductive traces with fine pitches is improved for the integration of the integrated circuits (ICs), and the need of thinner ICs package and higher input/output counts.
As shown in FIG. 1, a circuit substrate 10 mainly includes a board 100. The board 100 comprises a core board 101, a plurality of insulating layers 110 and conductive traces layers 130. The insulating layers 110 and the conductive traces layers 130 are interlaced with each other. The conductive traces layers 130 are electrically connected with each other through vias 140 such as through holes, buried vias or blind vias. Now taken a through hole for example as shown in FIG. 1, initially, the insulating layers 110 and the conductive traces layers 130, which are interlaced with each other, are penetrated to form a through hole therein by the method of mechanical drilling or laser ablation. Next, the inner wall of the through hole is electro-less plated with a copper film and then another copper layer is deposited on the copper film. Finally, the through hole is filled with an insulating material, for example epoxy and ink. Now referring to FIG. 2, via land 160 is disposed at the periphery of the via 140 to electrically connect the conductive traces 130a and the via 140. Generally speaking, if the diameter of the via 140 is about 300 μm, the diameter of the via land 160 will be about 500 μm. In addition, a landless design can be employed to save the area for the arrangement of the via land 160. However, the process of the landless design is complex and the cost is increased.
As shown in FIG. 2, the via lands 160 occupy a lot of areas so that the areas for laying out the conductive traces are reduced. In such a manner, the conductive traces 130a will be finer and the pitches between the conductive traces will be fined down. Consequently, it will be difficult to fabricate the circuit substrate. Besides, the quality of the electricity will be seriously affected in that, with reference to FIG. 2, the bent portions of the conductive traces and the distance of the signal transmission are increased.
As shown in FIG. 3, the previously mentioned problems can be solved and improved by directly reducing the diameter of via 240. Plasma, Nd:YAG laser and excimer laser can be utilized to form via 240 with smaller diameter. When the diameter of the via 240 is reduced, the areas for laying out the conductive traces 230a can be increased to reduce the bent portions of the conductive traces 230a. However, the fabrication method of plating metal layer on the inner wall of the via 240 will become more complex due to the smaller diameter of the via 240.